![FPGA Zealot](/img/default-banner.jpg)
- Видео 129
- Просмотров 151 948
FPGA Zealot
Добавлен 7 дек 2006
I work on FPGAs in industry, at school, and as a Hobby.
These videos are unpolished recordings of me developing my FPGA projects.
Feel free to ask questions!
These videos are unpolished recordings of me developing my FPGA projects.
Feel free to ask questions!
Xilinx FPGA PCIe Python Driver Development Part 3 (DDR)
Xilinx FPGA PCIe Python Driver Development Part 3 (DDR)
Просмотров: 988
Видео
Xilinx FPGA PCIe Python Driver Development Part 2 (Flash)
Просмотров 8163 года назад
Xilinx FPGA PCIe Python Driver Development Part 2 (Flash)
Xilinx FPGA PCIe Python Driver Development - Part 1
Просмотров 3,9 тыс.3 года назад
Xilinx FPGA PCIe Python Driver Development - Part 1
Xilinx FPGA PCIE QSPI Flash Reading
Просмотров 1,2 тыс.3 года назад
Xilinx FPGA PCIE QSPI Flash Reading
Xilinx FPGA PCIE Page DDR Interface
Просмотров 1,6 тыс.3 года назад
Xilinx FPGA PCIE Page DDR Interface
Xilinx XDMA and XVC for PCIe data and debugging
Просмотров 4 тыс.3 года назад
Xilinx XDMA and XVC for PCIe data and debugging
FPGA Video Processing Line Buffers #2
Просмотров 3634 года назад
FPGA Video Processing Line Buffers #2
FPGA Video Processing Line Buffers #1
Просмотров 4864 года назад
FPGA Video Processing Line Buffers #1
FPGA Video Processing Line Buffers #0
Просмотров 8214 года назад
FPGA Video Processing Line Buffers #0
FPGA Image Processing RGB 3x3 Kernel HLS
Просмотров 4574 года назад
FPGA Image Processing RGB 3x3 Kernel HLS
FPGA Image Processing 3x3 Kernel Demo
Просмотров 3514 года назад
FPGA Image Processing 3x3 Kernel Demo
please do more videos using nios v processor sir
Hi is it possible to do this installation if I have wsl
I think so
Another incredibly helpful stream. I was able to replicate pretty much all of this with 2024.1 toolchain and on a different versal part (VD100 from Alinx) down to every Vitis bug , the only things left is actually running it. Seems that booting your pdi with baremetal elf is the hardest part to get right (until you figure it out, that is). Also, the most important detail about linking aarchnone64.o - it would take forever if you didnt point it out.
i would be very interested if you can expand on this exercise - to run Linux (minimal) on a NIOSV soft-cpu on a DE0-NANO or other small board board. :)
I need to get better at Bitbake and Yocto for that... Maybe buildroot would be better
I didn’t even know there’s a pynq equivalent for Altera . Great stream !
That's just so impressive
I am using a ZCU216 board, I am able to follow the steps until the hardware is programmed. I am using SFP cage transceivers to create a loop back test. The issue is when I try and do program device and load the bitstream nothing comes up. I only see the SysMon and nothing from the IBERT. Am I missing something? Also I selected the internal clock.
I would suspect that one of clocks are not running correctly.
I am learning from you in few videos more than whole my bachelor and master. Big thank you
its very old, but i have one use it for video frame buffering for my hardware encoding and decoding
Hello Andrew, Thank you so much for this valuable information. I just have a question. You always mention and showing your designs in vivado during streaming but you never say any reference for them. Is there any chance that we can access them for learning purposes? Specially the one with PCIe, DDR and Microblaze. Thank you in advacnce
There will be better references for future videos. Feel free to use discord to ask specific questions. I'll try to backtrack references for older videos as well.
@@FPGAZealot You are the best ever, thank you so much. I will never miss any of your streams in the future
Just best stream ever. Big thank you for your time
That's a gigantic AXI 😂
Can you put like 16-32GB RAM into that SODIMM then load big LLM model into this ZCu104 ?
Yes that's possible, but you need to modify the Vitis AI design to use the PL DDR.
@@FPGAZealot So it used PS DDR by default? Sorry I have no Zynq or ZCU to test this.
@@thanatosor Yes
Mind uploading the design files to GH so we could understand what's going on a bit better? Because you're familiar with your code, you go through it quite fast, too fast. I also have a Zuboard (no m.2 adapter, though), so I'm also curious about how you've set it up for this test. I'd love to experiment with PCIe on both Xilinx and Altera platforms, but sadly my other FPGA is a DE10-std so that's not happening until an affordable Agilex 3/5 comes out
I post something. Feel free to join the discord to ask more questions.
I was totally excited to sit down and watch this walk-through as I am beginning to test the waters of a FPGA design. But FPGA Zell it appears to give us a video of him talking to himself in front of a camera. We are unable to read your thoughts so as you mouse around the screen making comments we are lost to what is going on in your head and what you are doing. I hope your future videos will have more of a explanation to what you are thinking as you look around the GUI.
I will try to think of ways to make the content easier to follow. Feel free to join the discord to ask question and post ideas.
Hello, first of all, thank you for your video, I would like to ask you a question. How can I find out how uBlaze-V kernel compares to regular uBlaze?
Why not demo in ZYNQ or Artix-7 based FPGA, since VERSAL is EE edition only, with 3,000$ license.
I have videos for the other platforms.
Your streams are so incredibly helpful even a couple years later… it’s too late now but any chance for future ones with better resolution then 720 ? Zooming in on text can be tough at 720
That was a mistake in that stream. New Versal stream later this month.
@@FPGAZealot what do you think about the $800-900 versal parts from Trenz and Alinx ? I’m waiting for the latter now, hopefully it’s not a lemon …
Thanks a lot man!
I am searching open-source RISC-V IP can fit it into AMD (soft-core) like microblaze, can you please prupose some link resources for that, or if you can live session , Thank you
I suggest LiteX
Thanks for your amazing contents. They are pretty helpful. Just how can i notify about your live sessions?
Follow on our Discord
Any chance of you getting a SoC and have the two sides (Nios V and ARM) talk with each other, and do whatever? It can be something simple, although you could slap on an SD a pre-built Linux image, if one exists for whatever board you got. Maybe even just run two identical codes simultaneously, and have one side signal to the other that it's done and compare the run times (maybe also include the time it takes to signal?) of the two. CycloneVs are cool. Waiting for cheap/educational Agilex devices to come out
I saw today they’re gonna ship an Versal SOM for around $800 which is basically free compared to every other Versal option
Hi Pynq lora please
@FPGA_Zealot please send the Github link of above project
I was hoping for like a Resnet-50 benchmark. any chance you know where i could find that?
They should have an example of it on the GitHub.
@@FPGAZealot i found their github for some sample code that will do the benchmark but no results and i didn't want to buy one just to do it lol
Thanks a lot for this stream ! I learned a lot of techniques which I never knew before !
What is your Linux machine configuration, like RAM and #CPUs?
Basic i5 6th Gen and 16 GB DDR 4
I may have missed that part but why do you wanna do microblaze if you have hard zynq us+ ?
Zynq in us+ is the PCIe Root Point; MicroBlaze is in the Artix and is the EndPoint of the PCIe.
How much is it?
$1300 ish
Thanks a lot for these live streams! Super helpful. I was getting the same error as you near the end even after pointing the launch.json to the BOOT.bin. After hours of head scratching, I realized I'd forgotten to enable access to the axi interrupt controller in the platform setup tab of Vivado. Keep up the great streams mate :)
Wonderful topic. Would you be interested to talk more on versal potential applications in space?
this board is so great!, can you help me how to buy it? thanks for your video
Contact Frontgrade
@@FPGAZealot yes, thanks so much!
Good talk on pcie on xilinx/amd
Nice yo
Very interested in the VE2302, this is most appreciated. Thanks for your efforts and to the group that donated it!
Thank you for being willing to make such detailed videos for such a niche subject. Every video I see uploaded by you catches my attention.
thanks so much, great video!
Is there a guide to run Linux on this board?
You could run Linux on the microblaze, but it would be slow and you would have to load the image over PCIe.
Did you ever figure out how to get RWEverything to access the memory addressed by your BAR?
Depends on the address space of the motherboard PCIe enumeration
@@FPGAZealot Did you get it working for your application? If you're able to get a configured BAR (which you can obviously check with RWE, or for that matter, even configure it with RWE), RWE should be able to access that address region the BAR points to I would think? I understand if the BAR is in 32 bit address space, on a 64 bit OS, that has to be mapped somewhere in the 64 bit address space. In my case, I just used 64 bit BARs, and I would think it would map it into real address space as far as RWE would think... I guess I'm assuming RWE memory read/write it to physical address in 64 bit space on a 64 bit OS.
I used WinDriver (Jungo) evaluation to make a .inf file for my board, used Device Manager to associate it with my board, and using Device Manager, did a scan for new hardware, and my board board got enumerated. Then I was able to read/write all the memory/GPIO registers behind the BARs. So, the answer is, RWE can access the memory behind my BARs.
Is it possible to do this on Xilinx Alveo U280 cards?
Yes, it is designed for those boards.
Real bad presentation skills. It might be better if it was done offline and edited, than in a live stream!
Hi bro, can you please make the video for testing performance in this project or any related PCIE project ?
keyboard name please
It sucks that they still sell these but havent updated anything to keep up with the open source tool chains. The make file is useless, at least on windows. Had to make a batch file that runs the commands automatically to generate the bitstream with the bootloader header. The ecp command failed because of the --compress flag is no longer valid. Nextnpr says there is no clock signal. So the program never runs, bootloader does, but nothing after. And to make things worse, i found out i dont even need a FPGA as there are apparently dedicated FIFO ICs. Might as well have just burned 100 dollars haha.
I should revisit this FPGA and give an update.
Hello Andrew, I am Zaid from Jordan, it is good to find your videos on RUclips, they are beneficial. I have a question regarding an FPGA project: I want to create an automatic driving system after knowing that the driver has fallen asleep or feels sleepy ... I want to implement it as a simulation project, not on a real FPGA device ... so what is the simplest and fastest way to perform it ... I'd like to let you know that I am still a beginner in the FPGA world.
Verilator is probably the simplest way for basic hardware simulation.
Thank you for the video, i learn from the video a lot.
I wonder how I can use an FPGA to speed up tasks like video encoding or other tasks that take a long time on the CPU and sometimes even GPU? As I wish FPGAs were much easier to buy, setup and use with apps I have on my PC. Is there a way this can be achieved or is the technology not there yet? I'm new to the FPGA scene.
The LiteFury 2 is the most affordable option, but the complete lack of HDL, driver, and API make it a hobby project at best. I plan to add some examples later in 2024.
It is possible to program these devices through PCI, I have one but I don't have any JTAG cables and I don't know what is loaded on it. Some say it has PCI to FLASH loader block from factory but how can you check?
The default image should have a method to write the flash, but if the image doesn't support it you will need JTAG.
@@FPGAZealot I think the factory image loaded does allow you to program using PCIe. I haven't really got into it but I guess I always have to account for PCIE > Flash access when uploading my rtl in case it goes to crap and need changes or new projects. This thing goes into homelab server which is controller remotely so flashing through PCI would be optimal. Thanks for your response, love your videos btw.
Thank you for this valuable video 😊
Please also try this with Alveo U280 board.