- Видео 17
- Просмотров 3 175
FPGAPS
Канада
Добавлен 5 июл 2024
Welcome to our channel! We are passionate about FPGA & Processing System Design and love sharing our expertise. We provide some trainings 🎬 that combine fundamental principles with hands-on design projects and practical implementation cases, and some personalized supports as well.
Some project materials and resources are available on our GitHub repository. Find it though "Links" 👇
If you find these materials helpful, please 👍 and subscribe to 🔔 our channel!
Feel free to comment 💬 with topics that interest you or any questions you have - we'll address them in future videos.
You can also connect with us on LinkedIn👇, where we regularly share the ideas and concepts behind our videos.
Some project materials and resources are available on our GitHub repository. Find it though "Links" 👇
If you find these materials helpful, please 👍 and subscribe to 🔔 our channel!
Feel free to comment 💬 with topics that interest you or any questions you have - we'll address them in future videos.
You can also connect with us on LinkedIn👇, where we regularly share the ideas and concepts behind our videos.
AXI DMA and Debugging with ILA Part 2: Vitis Design in Polling and Interrupt Modes
you can find the Vivado part design here:
ruclips.net/video/GAtmOTbOFNU/видео.html
This tutorial demonstrates how to implement and debug AXI DMA operations using Vitis and PYNQ platforms. The video covers three main implementations:
1. AXI DMA in Polling Mode using Vitis, where viewers learn how to:
- Set up a Vitis project using Xilinx GitHub repository examples
- Configure DMA transfers with TX and RX buffers
- Monitor DMA status through polling
- Debug the design using Integrated Logic Analyzer (ILA)
2. AXI DMA in Interrupt Mode, which explores:
- Implementing interrupt handlers for TX and RX channels
- Setting up interrupt-driven DMA transfers
- Observing interrupt signals through ILA debugging
-...
ruclips.net/video/GAtmOTbOFNU/видео.html
This tutorial demonstrates how to implement and debug AXI DMA operations using Vitis and PYNQ platforms. The video covers three main implementations:
1. AXI DMA in Polling Mode using Vitis, where viewers learn how to:
- Set up a Vitis project using Xilinx GitHub repository examples
- Configure DMA transfers with TX and RX buffers
- Monitor DMA status through polling
- Debug the design using Integrated Logic Analyzer (ILA)
2. AXI DMA in Interrupt Mode, which explores:
- Implementing interrupt handlers for TX and RX channels
- Setting up interrupt-driven DMA transfers
- Observing interrupt signals through ILA debugging
-...
Просмотров: 55
Видео
AXI DMA and debugging with ILA, part 1: Vivado design
Просмотров 1197 часов назад
This tutorial explores the implementation of AXI Direct Memory Access (DMA) in FPGA design using Vivado. The video begins with a detailed explanation of AXI DMA's architecture and its role in efficiently transferring data between DDR memory and programmable logic (PL), offloading the ARM core from heavy data movement tasks. viewers learn how to: Set up a basic Vivado project with Zynq UltraScal...
Vivado Simulation: Dynamic Interfacing a signal generator with a Python GUI
Просмотров 32День назад
Have you ever wondered how to create a fully interactive dashboard to control a VHDL simulation in real-time? I discovered a clever trick to dynamically control a Vivado simulation using Python! I designed a signal generator within Vivado and built a Python GUI to control it during simulation. Now, here’s where it gets interesting-I’d love to hear your ideas on different ways to achieve this. L...
Dual ARM Core Hello World Vivado-Vitis Application: Controlling the PL Using A53 and R5
Просмотров 9014 дней назад
Learn how to create a dual-core ARM application using Xilinx's Vivado and Vitis tools to control programmable logic (PL) with both A53 and R5 processors. The project features: A53 core running FreeRTOS controlling an blinking LED and monitoring a pushbutton R5 core running in standalone mode controlling a separate blinking LED and pushbutton AXI GPIO interfaces for LED control and push button m...
PYNQ AXI GPIO and Memory Mapped I/O (MMIO) Example: Control Blinking LEDs by DIP Switch
Просмотров 7221 день назад
In our previous Video we demonstrated how to: Create a Vivado design containing multiple AXI GPIO blocks. And Control these AXI GPIOs in Vitis using the Memory-Mapped I/O (MMIO) concept: ruclips.net/video/AbsUNeIYyiU/видео.html In this video, we will take it a step further by explaining: How to access and interact with peripherals directly in a Jupyter Notebook. Learn how to interface with AXI ...
AXI GPIO & Memory-mapped I/O (MMIO) : read/write to peripherals using a C pointer & control user I/O
Просмотров 127Месяц назад
Learn how to master AXI GPIO and memory mapped I/O on Zynq UltraScale devices in this tutorial! This video walks you through creating a complete hardware-software project that demonstrates how to control peripherals from ARM cores using memory-mapped I/O. The Vitis application read the DIP switch in polling mode and controls the LED shift pattern. In Part 1, you'll learn how to: - Set up a Viva...
Zynq Ultrascale+ Boot from QSPI and SD Card: Create Boot Image, Flash QSPI with Vitis & Vivado
Просмотров 215Месяц назад
Learn how to configure and boot your FPGA development board using QSPI Flash and SD Card. Key Topics Covered: Creating boot images in Vitis IDE Programming QSPI Flash using both Vitis and Vivado Boot mode switch settings for different boot options Setting up SD card boot option Serial terminal configuration for debugging You can watch our previous video for creating a "Hello World" project in V...
Hello World Application in Vitis: Creating and Building a Project, and Launching Bitstream on Device
Просмотров 223Месяц назад
Hello World Part 2 Vitis Project: This tutorial guides you through the process of creating and setting up a Vitis project for Zynq UltraScale development. The video covers: Setting up a new Vitis application project using an exported XSA file from Vivado Creating a standalone application using the Hello World template Understanding the Vitis project structure Building and cross-compiling the ap...
Hello World in Vivado: PL-PS Clock & Peripheral Setups & Board Files & Schematic Review & Export XSA
Просмотров 208Месяц назад
Hello World Part 1 Vivado Project: : Creating Your First Zynq UltraScale Design Learn how to create a basic Vivado design for the Zynq UltraScale MPSoC using the ZCU104 evaluation board. This step-by-step tutorial covers: Creating a new Vivado project with Zynq UltraScale IP Understanding board files and presets Reviewing the hardware schematic and matching it with the design. Building a simple...
Numerically Controlled Oscillator(NCO) Simulation in Vivado: Phase Accumulator and Block Memory(LUT)
Просмотров 236Месяц назад
Learn how to design and implement a Numerically Controlled Oscillator (NCO) in Vivado using a block design approach! This tutorial walks you through creating a variable-frequency sine wave generator using FPGA technology. Key topics covered: Implementing sign and phase sawtooth pattern with variable frequency Using Block Memory as a lookup table for sine coefficients Setting up a phase accumula...
Dual-Frequency Sine Generator: Implantation with Block Memory (LUT) and ILA Debugging
Просмотров 603Месяц назад
This tutorial demonstrates how to implement a sine wave generator on a Xilinx FPGA board using block memory as a lookup table. The video covers the complete implementation process, from initial design to final bitstream generation and debugging with ILA. Key topics covered: - Using the Xilinx Block Memory Generator in dual-port mode - Implementing different clock frequencies (100MHz and 200MHz)...
Dual-Frequency Sine Wave Generators in Vivado Simulation by Xilinx Block Memory Generator
Просмотров 388Месяц назад
This tutorial demonstrates how to effectively utilize the Xilinx Block Memory Generator in FPGA designs to create dual-frequency sine wave generators. The video walks through creating a design that generates two sine waves with different frequencies using block RAM as a lookup table. Key topics covered include: Block Memory Generator configuration in standalone native interface mode Dual-port R...
Vivado Implementation of Synchronous LED Shifter : Clocking Wizard + VHDL Module + I/O planning
Просмотров 151Месяц назад
What if we want to use only the Programmable Logic (PL) resources and run VHDL code to control some I/O ports? In this design, I intentionally avoided using the Processing System (Zynq UltraScale IP) block. This approach emphasizes utilizing an external clock source instead of relying on the clocks provided by the PS. Additionally, this example demonstrates the proper implementation of a synchr...
Using Vivado Clocking Wizard to generate different clock frequencies, MMCM & clock buffer explained
Просмотров 2052 месяца назад
This educational video demonstrates clock management techniques on the Xilinx ZCU104 FPGA development board, focusing on the Programmable Logic (PL) Fabric while bringing the clock form carrier card. Using the Clocking Wizard IP to generate two different clock frequencies (100MHz and 200MHz) from a 300MHz input clock Implementing a practical application that blinks two PL LEDs at different freq...
Zynq Ultrascale+ ZCU104 Board Overview Part3: Clock Resources & USB & Ethernet & SATA & DisplayPort
Просмотров 1402 месяца назад
In the third overview, we explore the board's diverse connectivity options and sophisticated clocking system. Key topics covered: PS-USB interface and USB-3 connector UART serial communication and USB JTAG Gigabit Ethernet capabilities M.2 SATA SSD support DisplayPort and HDMI interfaces Programmable and fixed clocking options
Zynq Ultrascale+ ZCU104 Board Overview Part2: DDR & QSPI and SD card & PMOD & FMC connectors
Просмотров 1532 месяца назад
Zynq Ultrascale ZCU104 Board Overview Part2: DDR & QSPI and SD card & PMOD & FMC connectors
Zynq Ultrascale+ ZCU104 Board Overview Part1: PL-PS resources & Video Codec & Configuration Options
Просмотров 2112 месяца назад
Zynq Ultrascale ZCU104 Board Overview Part1: PL-PS resources & Video Codec & Configuration Options
Hello, Can you please provide information on how to mount the M.2 SSD on the ZCU104 board. I have bought an M.2 SSD and connected it to the ZCU104 board, but when I type the lsblk command in the PYNQ terminal the SSD is not showing up. is there any steps to enable the SSD is so can you share that?
Thank you for your video. It is very useful for beginners
Hi, this is a great tutorial, I'm having trouble creating a platform project in vitis 2024. Do you have a solution ? I've exported the xsa successfully but vitis just doesn't allow creation of platform project even after choosing workspace
Hi welcome to our channel! Are you using the "Vitis classic" or new IDE? There are two shortcuts, one is "Vitis Classic 2024.1". the new IDE seams to have this bug, can you try with the classic one? Thanks
thanks for this great clip. my question is when I have 2 application code on each core for dualcore zynq. How I can do this procedure?
Welcome to our channel! We gonna explain it in our future videos, stay tuned!
7:48 FMC, can you run the loopback card in future videos ? Thanks
I like the way you explain XSA. Thank you!
Thanks! I didn't know we can run a simulation in Vivado that much easy! Is it possible to create a training for real Vivado implementation and synthesis please?
It's very clear! Love it!👍
😀 Thank you for the explanation. I/O pin planning part is quite interesting.
Glad you liked it!
Greate Video! Continue!
Thanks, will do!
Great!
Thank you! Very interesting!