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Please provide lecture for hold issues in some more details. Thank you very much for half cycle path concept.

Good

Good explanation sir. In the case of metastability YES, what type of waves will be there. And what is solution, apart from adding path in false path list?

Very good explanation

thank you bro

Very informative thank u

bro today i have exam but i am not able to not understading what to do

Your explanation very nice, please continue videos, it helped me to crak the interviews

Most underrated video ..... Superb explanation

Thankyou sir

Very easy explanation Sir , u made it seem very simple. Thank you

Thank you sir for your great explanation. Actually I have few doubts Is it mandatory to set the adding of input delay and output delay is 100% like 70% ,30% of time period of clock period. My clock period is 2ns. And When i am doing synthesis area of the design is changing with respect to input delay and output delays. I am increasing input delay area is also increasing and if decreasing area getting decreasing. how can we choose the delay values of input and output delay? where we will get these values. Could you please help with this sir?

sir how u took that setup is 3ns u assumed or u calculated

Design a sequence detector to detect three or more consecutive 1's in a sequence of bits using Mealy model

Where is done overlapping

thanks

Sir, Pl, make use of a DSLR. Auto focusing is made easy and the video quality will be good. Thank you.

thank you bhaiya.. thanks a lot

Really great🎉

🙌👏

Sir, At 11:18 For hold, we should check at launch flop itself, as you discussed in previous videos So buffer should add before launch FF not after launch FF? Plaese clarify this doubt, sir

for t_hold <= T_clk/2 --> no change in hold equation But for t_hold >= T_clk/2 then --> t_hold <= T_clk/2 + t_cq + t_comb

One small correction, sir 14:00 t_hold <= (t_cq + t_comb) <= (T_clk - t_setup) 1ns <= t_total <= (4-1)ns

Hi, what you have explained at 1st point for that path we can assign set_clock_groups -asynchronous also right ?? Please clear my doubt

Excellent

What you are telling is absolutely wrong. For half cycle paths hold check becomes relaxed by half cycle and for half cycle paths hold becomes frequency dependent. Please get your own concepts clear before teaching.

exam in 2hrs , this video cleared my concept last hour.

i dont understand about "out = 1'b0" 4 turn

Your english is very good like babar azam

Bro we want same explanation for hold So much confusion while doing it

Am I the only one who didn't understand a single thing

Excellent💯👍

thanks brother i seaching for this simple type of explanation, thanks for introducing it.

God literally ❤

How to know that when clock is reaching to other flops. lets say input side block. If time of clock is 10ns, and your calculated slack is 5.5 but on the other side if clcok reach to input side of flop at 6ns then 6+4.5 will be 10.5 and setup viloation happen.

If you do videos this much practically you will get huge success

Application orientated ga Videos inka chesi .. upload cheyandi sir

U r super sri

Can you continue your knowledge sharing... Why 🤔 you stop...?

Simple and best conversion bro !!! Thank you

For 1101 and 1100 What happens to the state s3 when it is 1 bit overlapping?

BUT THIS METHOD DOES NOT HELP IN FINDING MINIMUM NUMBER OF 2 INPUT NAND

I love the way you explained this..I wasn't able to understand this even after watching other videos but yours one cleared all doubts

Not able to follow with poor audio and images

Sir in 1100 during s1 cant we stay in s2 if it is 0 in stead of going to so

Awesome explanation....the most liked part in the lecture is explaining in practical way..

Thanks for the video! How does the command change when the flop is driving a port and the port goes into a flop with a different clock (assume clk_y which is a div/4 version of clk_m)? Will the command now be: set_output_delay 4.2 -clock clk_s [get_ports y]? What about the impact of the clock period at the destination?

sir at time frame 14:00 shouldnt it be 1ns < Total delay < (4ns-1ns) ?

Why should we create generated clk

Good explanation Sir. Thank you very much for the session.