why can't you just analyze it from the right side of the ckt? you know the input to right gate is also Vcm, so wouldn't the output just be a common source gain with drain resistance and source degeneration? E.g. gmro * (Rd/(ro + Rs + gmroRs)) .. if you calculate this then this basically becomes ro4/(2*Rss). Your calculation is 1/(2*Rss*gm4) instead though
Hi, sorry for the delayed response. As the circuit has a current mirror, in order to find the output voltage we need to consider the effects of all circuit components. If you consider only the left hand side of the circuit, the effects of current mirror n M1 will not be taken into consideration. That's why we first found icm and did the vo estimation. Hope I cleared your doubts. For any further clarification You can call me at +919620243260
explanation is good, but it'll be great and easy to understand the concept if you can clarify the concept with animation rather than just read the points as a pdf document. And more explanation is needed in understanding the concepts what is residue? what is the use of subtractor here in this pipeline ADC concept why we are dealing with DAC in every stages? give more detailed animated explanation on at least one stage of the pipeline ADC to understand it more clearly. Note: Students come to RUclips by spending their valuable time to grab whatever their looking for in a great detail or at least to grab the concept clearly, So don't make it seam as a conventional lecture in a college where a professors or teachers just hover around the theory.
Exactly , but I'm still not clear between coarse flash adc and fine flash adc , 2:05. For base 10 in addition to base 2. Fix ( from "Basic", Software ).
For the last example, since the video ended before revealing the final answer, Overall DAC output will be 01000011 and its corresponding Vout=1.3499V which is the final answer of the Subranging Flash ADC?
![Narasimhamurthy K. C. [VU3DWF]](/img/default-banner.jpg)
Common Source Amplifier with resistive load for gain GIVEN SPECIFICATIONS: Gain = 15dB CL = 2 pF Power = 2 mW GBW = 5MHz
What do you want..
Perfectly understood both inverting and non-inverting gain of both ideal and non-ideal op-amp😊✨
Thanks for clear explanation
Sir can you please make a video on how to calculate this bandwidth using ADK kit's network tab. I didn't get that part
Sure..
7:19, parasitic delays should add to N?? each inverter has p = 1.
Cc?
What Cc..
Super sir .... keep. Posting......people like you are only. Can.create Lead a. Healthy. Environment
how did you add Vc and op on your diagram
Use the Label net option on the tool bar and type the relevant name
why can't you just analyze it from the right side of the ckt? you know the input to right gate is also Vcm, so wouldn't the output just be a common source gain with drain resistance and source degeneration? E.g. gmro * (Rd/(ro + Rs + gmroRs)) .. if you calculate this then this basically becomes ro4/(2*Rss). Your calculation is 1/(2*Rss*gm4) instead though
Hi, sorry for the delayed response. As the circuit has a current mirror, in order to find the output voltage we need to consider the effects of all circuit components. If you consider only the left hand side of the circuit, the effects of current mirror n M1 will not be taken into consideration. That's why we first found icm and did the vo estimation. Hope I cleared your doubts. For any further clarification You can call me at +919620243260
The most useless video i have found till date for logical effort.
Thanks for your feedback. Will try to correct myself
Wgc2=155.94 r/s
Dear all, at 38 minute of the video there is a error in phase angel.. (mistake while typing in calculator 😮) Please correct it.. Please fix it..
This was an interview question for me. It was a new concept but I did end up getting Vg1 = delta(Vt)
Thank you 🙏 sir
Control system in 4th sem engineering ty sir
Sir can you please make a vedio on the topic of order of system I mean zeta topic, sir it is bit confusing so please sir make a vedio on that
Do you mean 2 nd order system.. with different damping ratio ..
@@narasimhamurthyk.c.vu3dwf475 yes sir
@@narasimhamurthyk.c.vu3dwf475 yes sir
Sir can you make a vedio on today's class problems
Those will be solved in the class only na... so..
Sir but last problems of zero and poles were confusing so can you make vedio on that topic please sir
Sure@@ChikkuK-z4p
@@ChikkuK-z4p will do the needful to clear the doubts
@@narasimhamurthyk.c.vu3dwf475 thank you sir
explanation is good, but it'll be great and easy to understand the concept if you can clarify the concept with animation rather than just read the points as a pdf document. And more explanation is needed in understanding the concepts what is residue? what is the use of subtractor here in this pipeline ADC concept why we are dealing with DAC in every stages? give more detailed animated explanation on at least one stage of the pipeline ADC to understand it more clearly. Note: Students come to RUclips by spending their valuable time to grab whatever their looking for in a great detail or at least to grab the concept clearly, So don't make it seam as a conventional lecture in a college where a professors or teachers just hover around the theory.
Surely
Sir the value of Rf in binary weighted R DAC is 200 ohm, not 220 ohm 28:59
Take it as 200 only... it's not a big issue
😃
can I add more parameters
Sir where can I find these questions?
really helpful
Best explanation, Thank you❤
Thank you so much 🙏 , wonderful explanation 😊
Thanks for this playlist 🙏🙏
Thank you
Professor, is there a lecture video of yours on the simulation of the same[1T DRAM] in LTSpice?
Will do and send it ..
Thank you, Professor.
Stanford ke lecturr ka copy mara hai
Is it... Good if the video is to Stanford level. I Never saw that video. If you feel its a copied one, its left you which one to see🙂. Thanks
Can you make more video like lt spice simulation op amp 3rd order 4th order
efforts 🤌
good video, i lke it. i wanted to know how i can transmit a white noise with the use of a NE555 ? do i need a VCO ? thank for your answer.
No it's not possible..using 555 timer
Thank you. The video helps me a lot.
Exactly , but I'm still not clear between coarse flash adc and fine flash adc , 2:05. For base 10 in addition to base 2. Fix ( from "Basic", Software ).
Thank you so much finally found a vedio that cleared my concept!
Audio is not clear please make new video with good audio
What is the logical effort of a NAND10 gate?
Please reply sir
For the last example, since the video ended before revealing the final answer, Overall DAC output will be 01000011 and its corresponding Vout=1.3499V which is the final answer of the Subranging Flash ADC?
Amazing! Please continue the good explanation for such circuits.
sir how can we compare and say ,that either long channel or short channel logical effort is greater based on numper of inputs
If we are getting sine wave but not with proper pulses, shape is distorted,how to resolve that??
sir, can we see the circuit?? or the source or the journal about it.. please..
Thank you! That was very helpful.
It helped to see the distortion on scope.
Good voice Nyc explanation Nxt level teaching🙏🏼
DIE NACHBARSCHAFTEN SIND LEIDER IN DEM VIDEO NICHT DA
Nice explanation.
For silicon diode the break down region is not showing
I am not getting the output like this.. i have done the same steps
Thanq sir